1. Field of the Invention
The present invention relates to a semiconductor device package having a mount structure and a semiconductor device mount method, and particularly to a semiconductor mount structure which can mount a semiconductor device thereon while having substantially the same size as the semiconductor device.
2. Description of the Related Art
This type of semiconductor device has been disclosed in Japanese Laid-open Patent Application No. Hei-7-509352.
In the semiconductor device mount structure disclosed in the above publication, a gap is provided in a sheet-shaped support structure to divide the support structure into a center portion and an external fix element through the gap. The center portion is provided with plural center terminals, and the external fix element is provided with plural external terminals. Further, a lead is provided to connect each of the plural center terminals and each of the plural external terminals to each other through the gap. The support structure is overlaid on the semiconductor device to connect plural electrodes disposed on the peripheral portion of the semiconductor device to the leads located on the gap of the support structure, thereby implementing the semiconductor device mount structure in which the electrodes, that is, the center terminals are provided so as to be located inwardly from the outer shape of the semiconductor device.
In general, a semiconductor device must be tested while mounted in a package, because it is difficult to perform detailed tests on the characteristics of the semiconductor device and the circuit operation thereof when it is tested as a single body. Accordingly, a jig such as a test socket or the like is easily detachably mounted.
However, according to the prior art described above, the center terminals are provided on the circuit surface or plane of the semiconductor device to electrically connect the semiconductor device to the external. Therefore, when a testing electrode is pressed against to the center terminals in a semiconductor device testing process after the semiconductor device is mounted, the press force of the testing electrode is directly applied to the circuit plane of the semiconductor device. For example, in the case where the number of the center terminals is equal to 100 and the press force which is necessary for the testing electrode to be conducted to the semiconductor device is equal to 50 g per terminal, the total press force is equal to 5000 g. Therefore, there is a risk that the semiconductor device is broken when the press force is applied to the circuit plane of the semiconductor device. As described above, the terminals are provided on the circuit plane of the semiconductor device in the above prior art, and thus the prior art has a problem that the terminals on the circuit plane of the semiconductor device has an adverse effect on the reliability of the package.
There is another test method which is different from the above test method. In this method, a package is mounted on a test substrate by soldering for test, and then the package is detached from the test substrate after the test is completed. However, this method needs not only long time and high cost, but also needs to increase the temperature of the package up to the melting point of the solder when the package is mounted on and detached from the test substrate. Therefore, the thermal history of the package itself is increased, and this has an adverse effect on the reliability of the package.